Fully depleted double gated FIN MOSFETs are an attractive choice for the 25 nanometer (nm) CMOS technology node, i.e. node design rule dimension of 25 nm and smaller, due to their good electrostatic characteristics, i.e., MOSFET device short channel effects, and very high on-current density. However, two issues arise from the use of FinFETs in the 25 nm and smaller design rule. First, the FIN thickness (t) must be smaller than 7 nm to realize improved device characteristics. Unfortunately, this results in a substantial reduction in the charge carriers mobility and device on-current due to device quantum effects, e.g., >50%. Second, if poly-silicon is used as the gate material, which is the CMOS process preferred choice, the fully depleted Fin MOSFET (FinFET) device will have a low device threshold voltage (Vt) and very high off-current. This results from the polysilicon (poly-Si) gate work function and the full depletion operation mode of the Fin MOSFET.